The March To Multicore Processors Continues
In the June 2025 issue of Aerospace Innovations, our story entitled “Multicore Processors: Why They Are Becoming Standard Equipment in Modern Avionics” explored the aircraft industry’s migration to these CPUs and away from single-core processors.
One year later, the migration to multicore has picked up speed. In this article, we see how multicore processors are being used in aircraft today, the issues that still have to be resolved with this technology, and how well multicore processors will support the advanced IT applications of tomorrow.
The Single-Core Drought
“The primary catalyst driving the aviation industry’s shift from single-core right now is lack of availability of single core parts,” declared Jay Thomas, Director of Field Engineering at TASKING, a company that provides embedded software development tools that support multicore systems across aerospace and other safety-critical industries. “Traditional processors used in aviation are shifting away and almost all of the newer generation are multicore.”
Gary Gilliland is Vice President of Marketing at DDC-I, a company that helps customers design, develop, and deploy critical avionics systems utilizing multicore processors. “Certainly, the lack of supply and the fact that all processor technological advances are going into multicore processors has an influence, but the avionics industry has considered multicore an attractive approach to improve upon processing performance and reduce system packaging wattage and cost for a long time,” he told Aerospace Innovations magazine. “Beyond the trail blazing by early multicore adopters in the aviation industry, recent accelerated multicore embrace is due in part to the industry’s understanding that tooling and software features can greatly simplify and reduce the complexities of multicore processing. These software features often also greatly improve upon real-time system performance—which then makes multicore processing even more appealing.”
It isn’t just supply problems that are driving the move away from single-core processors—it’s obsolescence. “A significant number of avionics functions and multi‑function systems, including graphics systems, can still operate effectively on single‑core processors,” said Olivier Charrier, a Principal Functional Safety Specialist at Wind River, a company that works with multicore processors in the aviation industry. “However, the phaseout of such architectures by silicon vendors means that multicore designs are now the only sustainable path forward. At the same time, multicore architectures present valuable opportunities to enhance existing avionics functions and extend capabilities toward greater autonomy. Advanced flight control, autonomy, and sensor‑fusion workloads simply exceed what a single core can support.”
Reality Check: Multicore Today
“Today, multicore processors power mission computers, flight control systems, and high‑performance compute nodes used for autonomy and advanced cockpit functions,” said, Michel Chabroux, Wind River’s Vice President of Product Management. “The hardware and software capabilities are mature and continue to be refined. Basically, all aspects of avionics are moving to multicore to be able to consolidate functionality and/or add capabilities.”
In fact, “Multicore processors are already ubiquitous in both civil and defence aircraft systems, but the majority of these have only a single active core,” said Dr. Sam Thompson, Multicore Engineering Team Lead at Rapita Systems, a company that delivers multicore engineering projects for its customers. “This is because using only one core per processor avoids a multicore certification process with EASA (AMC 20-193) and the FAA (AC 20-193). “This is an expensive, complex, and time-consuming process,” he told AI. “By taking a multicore chip and disabling all but one core, it behaves exactly like a legacy single-core processor. With no internal traffic jams to worry about, the safety certification process becomes exponentially easier and cheaper.”
From an engineering standpoint, it may seem wasteful to “dumb-down” multicore processors so that they act like single-core processors. However, “there can be a powerful advantage to employing a multicore processor in a single core application,” said Gilliland. “Once installed in the aircraft, the multicore processor can provide expanded processing capability in the future if the needs arise. We have cases where customers only need to modify the processor initialization and configure the RTOS’s multicore scheduler and off they go. They don’t even need to recompile their applications when converting their target from single-core to multicore processing. That’s a huge advantage.”
Proving Determinism in a Multicore World
Except during takeoffs and landings, computers fly modern aircraft. As a result, aircraft sensors, engine management systems, and flight controls all rely on Real-Time Operating Systems (RTOS) where a computer’s timing is just as important as its mathematical accuracy. If the Autopilot system calculates the correct adjustment for a flight control surface but delivers that command a fraction of a second too late, the result can be catastrophic.
This is why regulators like the FAA and EASA demand determinism from all onboard computers—the guarantee that a system will consistently complete a task within a strictly defined time limit. Avionics engineers must mathematically guarantee that a critical computer application will always hit its deadline, even under the absolute heaviest processing load. This metric is known as the Worst-Case Execution Time (WCET), and onboard computers must operate within it or better.
With legacy single-core processors, proving determinism was easy. This is because a single core has an uncontested single-lane road to the processor’s memory and data buses.
Because they share memory buses (the road), multicore processors can suffer traffic jams. When Core A (running a critical flight control task) and Core B (running a non-critical graphical display task) try to access the shared memory bus at the exact same microsecond, a traffic bottleneck occurs. Core B has to wait until Core A’s signal has gone down the lane. This wait time is referred to as “interference”.
Because interference creates unpredictable delays, the FAA and EASA cannot simply assume a multicore chip will act predictably. This is why AC 20-193 and AMC 20-193 certification processes exist, to prove to regulators that specific multicore processors running two or more cores simultaneously don’t suffer delays that could compromise critical avionics applications.
“Traditionally, the largest hurdle for multicore certification is viewed as ‘solving multicore interference’,” Dr. Thompson said. “However, this easily overlooks the less obvious but equally hard challenge of presenting the results of some very complex analysis in such a way that an airworthiness regulator can understand and have confidence in them. Doing this requires gaining access to sufficiently detailed documentation on the processor to facilitate analysis, at a time where there is a misalignment between different airworthiness regulators on acceptable means of achieving objectives.”
According to Thomas, the biggest hurdle to proving determinism and mitigating interference when certifying a multicore processor for onboard use is “understanding who owns what piece of the problem,” he said. “AMC 20-193 and its FAA counterpart AC 20-193 lay out clear objectives: Identify your interference channels, mitigate them, and prove through measurement that your mitigation works. However, they’re deliberately not prescriptive about how you do it. That flexibility is good, but it means every program needs to figure out its own approach, and that’s where teams get stuck.”
“The industry is overcoming this challenge through shared responsibility and better partnerships across the stack,” he continued. “Silicon vendors like Microchip with PolarFire are building hardware-level mitigation (i.e. TCM, core-local memory) directly into the processor. RTOS vendors like DDC-I and SYSGO provide temporal and spatial partitioning at the platform level. And tool vendors such as TASKING and its LDRA tool suite provide the measurement and analysis to verify that it all actually works, from WCET analysis, data and control coupling across cores, and traceability back to requirements.”
Single-Core on Death Watch?
Given the migration to multicore processors in avionics, are legacy single-core processors officially on a death watch? That’s a hard question to answer.
To do so, “We need to differentiate between ‘single core microcontrollers’ and ‘high performance processors’,” said Dr. Thompson. “Basic, low-power single core microcontrollers have been on aircraft—and everywhere else, for that matter—for decades, and will likely still be common when the eventual heat death of the universe rolls around. But for applications that require more processing throughput, every industry other than aviation migrated to multicore many years ago. So I don’t think it’s hyperbole to suggest that the high-performance single core processor is dead and buried in 2026.”
“Single‑core processors aren’t entirely gone, but they’re increasingly limited to narrow, low‑complexity roles—usually legacy hardware or systems with extremely simple compute needs,” Chabroux said. “They persist where determinism is trivial and there’s no incentive to re‑architect. Still, their long‑term viability is shrinking as suppliers discontinue single‑core lines. Wind River continues to support these legacy environments, but the momentum is clearly toward multicore platforms for anything forward‑looking or performance‑critical.”
“Today, truly single core processors are rare and will become niche over time,” said Thomas. “However, lock step matched processors where you have two cores and they can detect failed states provide value and act much like single core processors from the point of view for AMC 20-193/CAST 32A compliance. It is important to note that according to the standard, these should be treated as single cores, as both cores access memory simultaneously, and thus multicore contention is not possible.”
Powering the eVTOL Revolution
Electric Vertical Takeoff and Landing (eVTOL) aircraft are the Next Big Thing in Advanced Air Mobility (AAM), with many models being designed to be flown autonomously without human pilots. Achieving autonomous flight will require a tremendous degree of onboard computing power, and multicore processors will play a big role in supporting it.
“Multicore processing is not just important to AAM and eVTOL, it is a foundational architectural requirement without which the core safety case for these platforms cannot be constructed,” Gilliland said. “For autonomous operations, the sensor suite required for safe low-altitude flight, LiDAR, radar, cameras, GPS, et cetera generates continuous high data rate streams that are combined in real time to produce a reliable environmental picture for flight control decisions. Each sensor system operates at a different data rate and requires independent processing before fusion. Assigning these workloads to separate cores under ARINC 653 spatial and temporal partitioning is the only architecture that meets both the throughput requirement and the interference isolation required for DAL certification.”
“It’s essentially a prerequisite,” said Thomas. “Advanced Air Mobility (AAM) and eVTOL platforms are software-intensive by nature—you’re talking about fly-by-wire on vehicles that in many cases are inherently unstable without active flight control, plus you’re layering on battery management, power distribution, autonomy functions, and eventually detect-and-avoid for urban airspace. That’s a lot of compute for platforms where SWaP-C (Size, Weight, Power, and Cost) is absolutely critical because every gram and every watt affect range. You’re not going to meet those demands by strapping together a bunch of single-core boxes.”
The good news is that multicore technology allows eVTOL manufacturers to consolidate functions onto fewer processors, which directly supports the weight and power budgets these vehicles need to be commercially viable. “The challenge for AAM is that many of these companies are newer entrants who don’t have decades of DO-178C experience, and now they’re jumping straight into multicore with AMC 20-193 on top of it,” Thomas said. “That’s a steep learning curve. But the alternative of trying to build these platforms on legacy single-core architectures simply isn’t realistic given what’s available in the market and the performance these systems require.”
Meeting the AI Mandate
AI and machine learning applications are making their way into aviation, to enable autonomous flight, support predictive maintenance by analyzing aircraft sensor data in real-time, and reduce the in-flight workload of human pilots. Once again, this mission cannot be fulfilled without the use of multicore processors.
“AI and machine‑learning applications thrive on parallel processing, making multicore a natural fit,” said Chabroux. “Whether performing local inference, real‑time sensor fusion, or predictive diagnostics, these workloads demand significant compute horsepower. Multicore provides that capacity while enabling isolation between AI tasks and safety‑critical control loops.”
“Multicore is almost always inherent in AI applications,” Thomas added. “These cores could be a GPU or could be a CPU. In these high performance, memory intensive applications, multicore interference with potentially hundreds of GPU cores becomes impossible to characterize. Instead, what we have seen is more of a system view of the interference, motivating designers to adopt redundancy to characterize interference and improve reliability. Because the interference becomes inherently stochastic (driven by random probability rather than predictable math) with this many cores, using multiple instances of the same system for AI processes is a good way to make sure that it can provide an answer in a bounded amount of time.”
Dr. Thompson tempered this enthusiasm by touching on three key concerns. First, “how many years elapsed between the first commercial multicore processor and the first civil certification of one at DAL A (Design Assurance Level A)?” he asked. “About two decades. So we shouldn’t be surprised that the majority of the interest we see in flying machine learning models is at DAL C/D, or largely experimental and speculative. Second, while a multicore processor is far better-suited to hosting these large matrix-based models than a single-core, they are eclipsed by general-purpose graphics processors, and more recently by dedicated hardware acceleration modules. Most current projects we have using large machine-learning models are depending upon such hardware accelerators rather than multicores. And third, while airborne machine learning at high criticality is still some way from reality, these technologies are being actively investigated and deployed across the industry to accelerate existing workflows and provide efficiencies.”
The Elephants in the Hangar
So far, we have examined the trends and possibilities driving aviation’s migration to multicore processors. But what issues is the aviation industry not talking about when it comes to multicores and modern aircraft? What are the ‘elephants in the hangar’?
“The non-technical aspects,” replied Dr. Thompson. “I can design the most sophisticated battery of tests for a multicore processor, but ‘tis all for nought unless I can report the results in a human-readable way. I can throw the best engineer on the planet at a multicore processor, but they’re incapable of progress if the right NDAs to allow them access to the right information aren’t in place.”
“One topic not often discussed is the long‑term sustainment complexity associated with multicore,” Charrier told AI. “As hardware evolves rapidly, keeping a certified configuration stable for decades is a major challenge, particularly when hardware acceleration via GPUs or NPUs is introduced. While most SoCs provide mature hardware mechanisms for multicore CPU partitioning, equivalent isolation and partitioning support is often lacking for GPUs and NPUs. As a result, these accelerators are typically constrained to a single virtual machine or guest, which further complicates system architecture, integration, and long‑term certification sustainment.”
Perhaps the biggest elephant has to do with solving the multicore processor determinism and interference questions once and for all, through a concerted, open, and industry-wide effort.
“We need to move past treating multicore as a science project,” concluded Thomas. “There are programs out there that have spent years in open-ended interference research, characterizing every possible interference scenario, exploring every theoretical edge case, and all without ever converging on a bounded, certifiable solution. That kind of unbounded analysis can consume enormous amounts of time and budget, and at the end you still don’t have a shipping product. The question shouldn’t be, ‘can we fully characterize every interference channel in the abstract?’ It should be, ‘can we define a practical mitigation strategy, measure it, demonstrate compliance, and get this system certified?’”
By James Careless
